Hey, I'm

Brian Law.

Electrical Engineering student @ UIUC

I'm a junior studying Electrical Engineering at the University of Illinois Urbana-Champaign. I enjoy building at the intersection of hardware and software — from implementing System-on-Chip designs on FPGAs to designing custom PCBs with embedded firmware. I'm passionate about RF systems, digital design, embedded systems, and working on exciting hardware projects.

FPGA / Digital Design Embedded Systems PCB Design SystemVerilog C / Firmware UIUC ECE

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Work

Projects

NES Emulator on FPGA ECE 385

Spartan 7 FPGA · SystemVerilog / Verilog · C (MicroBlaze)

Super Mario Bros running on the FPGA NES emulator

For my ECE 385 (Digital Systems Lab) final project, I implemented a fully functional Mapper 0 NES emulator as a System-on-Chip on the Spartan 7 FPGA (Urbana Board). The design accurately replicates the original NES hardware — including the Ricoh 2A03 CPU and Ricoh 2C02 PPU — and was demonstrated playing Super Mario Bros and Donkey Kong via HDMI output with a real NES controller over USB. I was selected as one of ten projects to be demonstrated at the ECE 385 Final Project showcase.

            
            Modified open-source 6502 CPU core to replicate the Ricoh 2A03, adding a clock-enable signal to run at 1.789 MHz within a single clock domain
          

            
            Designed the Ricoh 2C02 PPU from scratch in SystemVerilog — full background & sprite rendering, scrolling (v/t/x/w registers), NMI, and OAM DMA state machine
          

            
            Built a memory-mapped bus arbiter routing CPU accesses to PRG ROM, CHR ROM, CPU RAM, PPU registers, and controller ports
          

            
            MicroBlaze soft-processor loads game ROM over AXI BRAM and polls USB HID controller input via the MAX3421E chip
          

VGA → HDMI output at 256×240 @ 60 Hz using HDMI TMDS IP

            
            5,593 LUTs · 4,035 flip-flops · 68.5 BRAM blocks · 117.7 MHz max frequency · 0.41 W total power
          

SystemVerilog Verilog MicroBlaze AXI Vivado Vitis FPGA SoC HDMI/VGA

brianlaw10/Spartan-7-NES

Bluetooth Iron Man Helmet ECE 395

STM32WB07 · 4-layer PCB · BLE / SPI / USART · C Firmware

PCB with OLED HUD displaying time over BLE

For ECE 395 (Advanced Digital Projects Lab), I designed and built a wearable Iron Man helmet featuring a Bluetooth-enabled heads-up display, a motorized visor, and eye LEDs — all driven by a custom 4-layer PCB. The HUD displays live time and iPhone notifications over BLE, projected through a beam-splitter and magnifying lens assembly into a 3D-printed Iron Man faceplate.

            
            Custom 4-layer PCB: dedicated GND plane, power plane (3.3V / 6V / 12.5V / VBAT), and isolated routing zones for sensitive BLE/SPI vs. noisy motor/SMPS circuitry
          

            
            STM32WB07 MCU with analog LPF matching network for the onboard BLE antenna; pairs with iPhone via ANCS (notifications) and CTS (current time)
          

            
            1.54" OLED display (SSD1309) driven over SPI; custom framebuffer, font LUT, and flipped orientation for the beam-splitter optical path
          

            
            Buck converter (7.4V→6V, 3A) + boost converter (6V→12.5V) + LDO (6V→3.3V) power tree from a 2S1P LiPo battery
          

            
            MG90S servo motors controlled via software PWM (SysTick) for visor open/close; capacitive touch sensor for user input
          

MOSFET-driven LED eye strips; entire system ≈75 mW (excluding motors/LEDs)

STM32 BLE / ANCS / CTS PCB Design KiCad SPI OLED Buck/Boost C Firmware 3D Printing

Background

Experience

May – Aug 2026
Sterling, VA

Embedded Systems FPGA Intern

CACI International

During my internship at CACI, I validated an RF tuner front-end module for production design candidacy, authoring formal test documentation including system block diagrams, test configuration BOMs, signal chain setup procedures, and step-by-step characterization test plans. I characterized SNR, SFDR, and frequency response across variable input frequency and power to define the tuner's ideal operating range and confirm its performance matched final design specifications. I also developed a 100 GbE core interfacing a ZCU208 RFSoC with a host PC, enabling Forward Error Correction through modifications to the PetaLinux image and migrating the design from Vivado/PetaLinux 2022.2 to 2024.2.

FPGA (ZCU208) PetaLinux RF / Signal Chain Test & Validation ARM Defense Tech

Aug 2025 – Present
Urbana, IL

Course Assistant — ECE 110

University of Illinois Urbana-Champaign

As a CA for UIUC's introductory circuits course, I host office hours, assist TAs during labs with 30+ students, and grade homework. The course covers foundational topics including Thévenin/Norton equivalent circuits, BJT and MOSFET behavior, and general circuit analysis — and working through these concepts with students has deepened my own understanding of the material.

Teaching Circuit Analysis BJTs / MOSFETs Mentorship

Brian Law.

Projects

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